In the field of design and manufacture of semiconductor devices, it is well known in the art that mechanical stresses in a substrate of a device may affect performances of the device, and stress engineering plays an important role in improving device performances. For example, during the manufacture of a field effect transistor (FET), such as a complementary metal-oxide-semiconductor (CMOS) FET device, stresses are generally applied to a channel region in the substrate of the device so as to improve mobility of electrons or holes therein. The mobility of electrons or holes in turn may increase an operational speed of the device, among other things. As is also known in the art, stresses are generally applied and/or engineered differently toward devices of different types. For example, the applied stress may be different depending on whether a device is a p-type FET (PFET) device or an n-type FET (NFET) device.
As far as a PFET device, for example a PFET gate, is concerned, it is common to design a longitudinal compressive stress into a channel region in the substrate under a gate area of the device. As an alternative, a nitride film or layer of nitride film may be deposited on top of and covering the PFET device. The deposited nitride film, due to its high intrinsic compressive stress, may externally induce stresses into the targeted channel region of the device such that a similar stress level may be achieved. The compressive nitride film or layer of nitride film may be formed through, for example, a deposition process such as a plasma-enhanced chemical vapor deposition (PECVD) process, and the film formed is usually conformal in shape.
As is also known in the art, during nitride film deposition through PECVD process, pinch-offs may occur around an upper section of the film deposited. The pinch-offs may cause voids to be created inside and/or underneath the film, which may inadvertently become leakage paths, during a subsequent metallization process, between closely spaced FET gates underneath the film. Although the formation of the leakage paths may be, to some extent, mediated through an improved process known as a modified reactive ion etching (RIE), which is described below in detail, aggressive scaling in device size in the semiconductor industry and increased complexity of device processing may continue to reduce and/or eventually eliminate any effectiveness and/or efficiency that this modified RIE may currently have in preventing the formation of pinch-offs, voids, and/or leakage paths. In addition to “void” as described above, deposition of nitride film through a PECVD process may also cause the forming of “tunnels” in a nested poly-contact (PC) structure around areas where source and/or drain interfaces with gate of the device. Similar to voids due to pinch-offs, “tunnels” may be filled with metal elements in a subsequent metallization process to become leakages or short paths as well. The leakages or short paths between different areas or regions of a semiconductor device may cause degradation of device performances and/or total failure of the device.
Also known in the art is a high-density plasma (HDP) deposition process that may be applied in producing compressive nitride films covering PFET devices. The HDP nitride process has been used in depositing copper (Cu) cap layers associated with a back end of the line (BEOL) technology. The HDP process typically uses a low frequency (LF), for example about 400 kHz, power source to generate an environment filled with plasma. The plasma is then deposited onto the surface of semiconductor devices to form a film. The semiconductor devices are generally biased. For example, to create a nitride film of compressive stress, the semiconductor devices on a substrate of 300 mm wafer may be biased at a fixed power around 400 W, which is equivalent to a fixed power density of about 0.5 W/cm2. The power source is typically a high frequency (HF) power source at around 13.56 MHz. It has been shown experimentally that the fixed bias power density, at 0.5 W/cm2 for example, may create a highly compressive nitride film with a stress level as high as −3100 MPa. However, it is also known in the art that a nitride film formed under this fixed bias condition for the purpose of generating very high stress level may also create “seams” around such regions as, for example, interfacing regions between a gate and spacers around the gate, wherearound the underlying gate structure may exhibit a nominal structural changes. In addition, the HDP deposition process, which is aimed for creating highly compressive nitride film, also generates voids caused by pinch-offs as described above with regard to the PECVD process.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity.